美光10月21日技术研讨会公开了垂直高带宽内存（vHBM）路线图：现有HBM在中介层上与计算芯片并排，vHBM则把内存叠到计算芯片上方；定制基础芯片可结合内存与计算逻辑。官方第22页把第一代vHBM目标量产放在2028年，并明确时点和性能方向可能改变。这次可确认的新事件是路线图披露，还不是现货产品上市。同场的G11 NAND计划采用晶圆对晶圆键合、超过400层结构，目标在2027年下半年放量。

At its technology webinar on October 21, Micron disclosed a roadmap for vertical high-bandwidth memory, or vHBM. Conventional HBM sits beside a computing chip on an interposer; vHBM stacks memory above the computing chip, and a customized base die can combine memory and computing logic. Slide 22 of the official presentation places the target for first-generation vHBM volume manufacturing in 2028 and explicitly says that the timing and performance direction may change. The confirmed new event is disclosure of a roadmap, rather than the launch of an in-stock product. The G11 NAND discussed at the same event is planned to use wafer-to-wafer bonding and more than 400 layers, with a volume ramp targeted for the second half of 2027.

我们的理解是，这轮变化把内存供应商更深地带入加速器设计。推理时若计算单元经常等待数据，缩短互连路径、提高每瓦带宽可能减少等待；但收益取决于具体模型、缓存和整机瓶颈。混合键合用于实现更密集的连接，基础芯片、封装和散热也必须一起设计。图中还保留了旁边的HBM，说明垂直堆叠可以与既有布局结合，不能据此推断原有HBM将立即被替代。

Our interpretation is that this change brings memory suppliers more deeply into accelerator design. If computing units frequently wait for data during inference, shorter interconnects and greater bandwidth per watt may reduce waiting time. The benefit, however, depends on the model, cache and bottlenecks in the full system. Hybrid bonding enables denser connections, while the base die, packaging and cooling must be designed together. The diagram also retains HBM alongside the computing chip, indicating that vertical stacking can be combined with existing layouts; it does not imply that conventional HBM will immediately be replaced.

官方图把带宽、能效和容量并列为影响因素，纵轴没有可复现的绝对刻度，并注明位置仅作示意；不能把线条高度读成相对HBM5的提速倍数。更密集的堆叠还需要解决热阻、互连、良率和可靠性，厂商列出技术方向不等于这些问题已获量产验证。G11的密度和接口指标属于芯片技术目标，不能直接换算成整块SSD或AI服务的速度；本文没有独立测量结果，也没有验证客户采用规模。此次材料没有给出可复现实验配置，也未公布这套垂直堆叠方案的普遍购买渠道，因此不能把研发方向写成已经规模部署的服务器能力。

The official chart presents bandwidth, energy efficiency and capacity as contributing factors. Its vertical axis has no reproducible absolute scale, and the positions are labeled as illustrative. The relative heights of the lines cannot be read as a speedup multiple over HBM5. Denser stacking also creates challenges involving thermal resistance, interconnects, yield and reliability. A vendor listing a technical direction is not evidence that those challenges have been validated in volume production. G11's density and interface metrics are chip-level technology targets and cannot be translated directly into the speed of an entire SSD or an AI service. This article contains no independent measurements and does not establish the scale of customer adoption. The material does not provide a reproducible experimental configuration or a broadly available purchasing channel for the vertical-stack design, so the development direction should not be described as a server capability already deployed at scale.

后续先看vHBM样品、客户认证、接口和功耗规格，再看目标量产时间能否兑现。有效比较应固定模型、精度、并发和容量，同时报告整机能耗、请求延迟、持续吞吐及温度；只有这样才能分清内存互连收益与其他升级的贡献。G11则要追踪真实出货、可用容量、寿命及SSD级测试。若只能展示封装示意而缺少持续运行数据，现阶段价值应仍归入研发与产业协作进展。

The next evidence to examine is vHBM samples, customer qualification, interface and power specifications, and whether the target manufacturing date is met. A meaningful comparison should hold the model, numerical precision, concurrency and capacity constant while reporting full-system energy use, request latency, sustained throughput and temperature. Only then can the benefits of the memory interconnect be separated from those of other upgrades. For G11, the relevant milestones are actual shipments, usable capacity, endurance and SSD-level tests. If the evidence remains limited to packaging illustrations without sustained operating data, the present value should still be classified as research progress and industry collaboration.